1. Field of the Invention
The present invention relates to digital filters that are used for digital audio devices in order to execute digital data separation and/or synthesis.
2. Description of the Related Art
A Finite Impulse Response (FIR) type digital filter is constructed so that output data Y(n) will be produced by convoluting input data X(n) and impulse responses, as expressed by equation (1). ##EQU1##
where, h(k) is a filter coefficient and N is the number of taps. When transformed with regard to Z, the equation (1) will be as follows: ##EQU2##
The equation (2) will be further transformed as follows: ##EQU3##
The equation (3) determines a frequency response. Assuming that .omega.=2.pi.k/N, the equation (3) will be as follows: ##EQU4##
This equation (4) may be regarded as an expression of Discrete Fourier Transformation (DFT). Thus, the filter coefficient h(k) is obtained through Inverse Discrete Fourier Transformation (IDFT) of the frequency characteristic given by the equation 4.
FIG. 1 shows the circuit of a standard FIR type digital filter.
In this filter circuit, a plurality of delay elements 1, which may be, for example, shift registers, are connected in series with each other and each of these elements delays the input data X(n) a certain period T. This circuit also has a plurality of multipliers 2, the first multiplier connected to the input data X(n) carrying line to the first delay element 1 and the remaining connected to the output line from each delay element 1. The first multiplier 2 multiplies the input data X(n) by a given filter coefficient h(k) and the remaining multipliers 2 multiply the output from each delay element 1 by the same filter coefficient h(k). In this way, the input data X(n) is convoluted with the impulse responses.
A total sum adder 3, included in this circuit, sums up the outputs from all the multipliers 2, that is, the input data X(n) and the outputs from all delay elements 1 after being multiplied by the predetermined filter coefficient h(k), and produces output data Y(n). Consequently, the input data X(n) has now been processed, subject to the arithmetic operation in compliance with the above-mentioned equation (1).
Because an array of delay elements 1 and multipliers 2, corresponding to the number of taps N are required, this type of digital filter has a problem that its entire circuit size becomes larger as the number of the taps increases. Therefore, a digital filter using a stored program method has been proposed which stores time-series input data in a memory once and sequentially multiplies the input data by the filter coefficient after reading it from the memory, while accumulating the product of each multiplication.
FIG. 2 shows a block diagram representing the digital filter using the stored program method.
In this block diagram, a RAM 11 sequentially stores time-series input data X(n) that has been input to it from moment to moment. A plurality of filter coefficients h(k) are stored in a ROM 12. Input data X(n) stored in the RAM 11 is read out at its arithmetic step and from the ROM 12 a step-specific filter coefficient h(k) with a value of k incrementing step by step is read out, where k corresponds to the k described in equation (1). Then, a multiplier 13 multiplies the input data X(n-k) read from the RAM 11 by the filter coefficient h(k) read from the ROM 12.
An accumulator 14, consisting of an adder 15 and a register 16, accumulates the product of each multiplication executed by the multiplier 13. Specifically, the adder 15 adds the output from the multiplier 13 and the output from the register 16 and the resultant sum is stored into the register 16 again. In this way, the product of each multiplication executed by the multiplier 13 is heated up sequentially. An output register 17 receives an accumulation value output from the accumulator 14 and outputs it as output data Y(n).
After reading the input data X(n) and the filter coefficient h(k) sequentially from the RAM 11 and ROM 12, respectively, the FIR type digital filter repeats the product sum arithmetic operation and produces the output data Y(n), thus processing the arithmetic of equation (1). This type of a digital filter does not become large, even if the filter circuit includes a large number of taps N.
One digital filter is assumed to have the first filter coefficient h1(n), whereas another digital filter is assumed to have the second filter coefficient h2(n) given by the following equation: EQU h.sub.2 (n)=(-1).sup.n -h1(n) (5)
The latter digital filter is referred to as a mirror filter because of its frequency response characteristics. The arithmetic relation of this filter with Z transformation can be expressed as follows: ##EQU5##
When we consider the frequency response characteristics of the filter, the following equation is obtained: EQU h.sub.2 (n)=e.sup.j.pi.n.multidot.h.sub.1 (n) (7)
When equation (7) is assigned to equation (6), the following equation is derived: EQU H.sub.2 (e.sup.j.omega.)=H.sub.1 (e.sup.j.omega.+j.pi.) (8)
From equation (8), the frequency response characteristics of the mirror filter are symmetric with regard to .pi./2. Because .pi./2 is 1/4 of the sampling period, the mirror filter is called a Quadrature Mirror Filter (QMF). A QMF of this kind is detailed in a publication "IEEE Transactions on Acoustics Speech and Signal Processing" (Vol. ASSP-32, No. 3, Jun., 1984, pp. 522-531).
A separation filter in which the above-mentioned QMF separates the input data into frequency components in different bands is constructed to produce two output data Ya(n) and Yb(n) which have been separated from the input data X(n). This filter convolutes the input data X(n) with the impulse responses and executes adding and subtracting calculations on the data obtained from the convolution process, as expressed by equations (9) and (10). ##EQU6##
FIG. 3 shows a block diagram representing the structure of the separation filter in which data separation into different frequency bands is performed according to equations (9) and (10).
As shown in this block diagram, a plurality of delay elements 21 are serially connected and each of these elements delays the input data X(n) a certain period T. Of a plurality of first multipliers 22, one is connected to the input data X(n) carrying line to the first delay element 21 and the remaining multipliers 22 are connected to the output line from each of the delay elements 21 located in the even number stages. The first multipliers 22 multiply the input data X(n) and the outputs from these delay elements 21 by a filter coefficient h(2k). There are also a plurality of second multipliers 23 connected to the output line from each of the delay elements 21 located in the odd number stages. The second multipliers 23 multiply the outputs of these delay elements 21 by a filter coefficient h(2k+1). In this way, the input data X(n) is convoluted with the impulse responses.
A first total sum adder 24 sums up the outputs from all first multipliers 22 and outputs intermediate data An. On the other hand, a second total sum adder 25 sums up the outputs from all second multipliers 23 and outputs intermediate data Bn.
A subtracter 26 subtracts the intermediate data Bn supplied by the second total sum adder 25 from the intermediate data An supplied by the first total sum adder 24, and outputs the first output data Ya(n). An adder 27 adds the intermediate data An supplied by the first total sum adder 24 and the intermediate data Bn supplied by the second total sum adder 25 and outputs the second output data Yb(n). In this way, the filter circuit accomplishes the arithmetic operation in compliance with the equations (9) and (10).
On the other hand, a synthesis filter in which the above-mentioned QMF synthesizes the input data frequency components existing in separate bands is constructed to produce an output data Y(n) into which the input data Xa(n) and Xb(n) are combined. This filter convolutes the values obtained by adding and subtracting calculations on the first and the second input data Xa(n) and Xb(n) with the impulse responses, as expressed by equations (11) and (12). ##EQU7##
FIG. 4 shows a block diagram representing the structure of the synthesis filter in which the synthesis of separate frequency bands is performed in accordance with the equations (11) and (12).
As shown in this block diagram, a subtracter 31 subtracts the second input data Xb(n) from the first input data Xa (n) and an adder 32 adds the first and the second input data Xa(n) and Xb(n). A changeover switch 33 alternately switches the output between the output from the subtracter 31 and the output from the adder 32.
A plurality of delay elements 34 are serially connected and each of these elements delays the output from the subtracter 31 or the output from the adder 32 a certain period T. Of a plurality of first multipliers 35, one multiplier 35 is connected to the output line from the switch 33 and the remaining are connected to the output line from each of the delay elements 34 located in the even number stages. The first multipliers 35 multiply the switch 33 output and the outputs from these delay elements 35 by a filter coefficient h(2k). Also included are a plurality of second multipliers 36 connected to the output line from each of the delay elements 34 located in the odd number stages. The second multipliers 36 multiply the outputs of these delay elements 34 by a filter coefficient h(2k+1). The main filter circuit section described above allows the values obtained by adding and subtracting calculations on the first and the second input data Xa(n) and Xb(n) to be convoluted with the impulse responses.
A first total sum adder 37 sums up the outputs from all first multipliers 35 and outputs intermediate data An. On the other hand, a second total sum adder 38 sums up the outputs from all second multipliers 36 and outputs intermediate data Bn. A changeover switch 39 alternately switches between the intermediate data An and the intermediate data Bn in synchronization with the changeover switch 33 and outputs the output data Y(n). In this way, the filter circuit accomplishes the arithmetic operation in compliance with equations (11) and (12).
The Applicant previously proposed constructing the separation and synthesis filters described above by using the above-mentioned stored program method. The details of this proposal are disclosed in Japanese Patent Laid-Open Publications No. Hei 6-216715 and No. Hei 7-131295.
For audio devices such as mini-disc (MD) players, data separation is executed when recording sound in order to separate audio data consisting of mixed different frequency components into data components in their specific frequency bands. Also, data synthesis is executed when reproducing sound in order to return a plurality of data to read which have been recorded in their specific frequency bands to the original form of the audio data. Therefore, such device is designed to operate as follows. In sound recording mode, using a separation filter as shown in FIG. 3, the device separates the audio data into data components in their specific frequency bands and compresses each separated data before recording the data into a recording medium. In sound reproducing mode, using a synthesis filter as shown in FIG. 4, the device synthesizes a plurality of data to read which has been expanded after read from the recording medium and produces the output.
Such a device enabling both sound recording and reproduction is required to have both separation and synthesis filters, which creates a problem that circuit size is made larger. Even if the QMF based on the above-mentioned stored program method is used, two sets of multipliers and accumulators are required and it is difficult to reduce the overall circuit size.